Two ways exist by which data can be communicated from a transmitter to a receiver: asynchronously or synchronously. Data communication is asynchronous when the transmitter and receiver employ separate time bases (clocks). While asynchronous data communication dispenses with the need for a synchronizing master clock signal to be transmitted with the data, the data instead is required to be bounded by control bits and typically buffered at both the transmitting and receiving ends. The control bits and buffering result in an overall reduction in data transmission rate.
Synchronous data communication occurs when the transmitter and receiver share the same time base. Synchronous data communication greatly reduces the need for buffering as described above and may simply utilize control bits for adding quality of service. Synchronous data communication, however, requires a master clock signal to be shared between the transmitter and receiver to ensure that they work harmoniously. While asynchronous communications systems have certainly found their place today, modern telecommunications systems and sophisticated computer networks predominantly use synchronous data communication due to the superior speed it offers.
Unfortunately, communicating a clock signal over distances can be challenging. A clock signal may be encoded in a square waveform and may be transmitted many miles over an electrical wire, optical fiber or wirelessly. The clock signal may be distributed with synchronous data or via a separate master clock network. In addition, the clock signal may be embedded within the synchronous data and extracted when needed. During its transmission, interference and transmission line impairments may serve to attenuate, disperse, distort and/or frequency-shift the clock signal, rendering it difficult to use or perhaps even to recognize at its destination.
Accordingly, it has become commonplace to employ circuits either to regenerate the master clock signal or use it merely to synchronize a local clock. Such local clock generating circuits often employ a phase-locked loop (PLL).
Modern communication systems demand high clock rates (to support rapid data communication) and high quality clock signals (often measured in terms of frequency excursion, or “jitter”) Modern communication standards typically specify low jitter bandwidths with respect to actual data rates which are employed. Accordingly, today's local clock generating circuits have grown more complex and expensive. Complicating matters is that the circuits may be called upon to generate local clock signals over a broad spectrum of frequencies. Such circuits should therefore be “frequency-agile.”
To date, several different approaches have been tried in an effort to achieve inexpensive, reliable, frequency-agile local clock signal generating circuits. One approach uses a relatively narrow bandwidth PLL in combination with a voltage-controlled crystal oscillator (VCXO). Although having the ability to generate high purity low noise clock signals, VCXOs cannot be integrated with PLLs on the same chip, are expensive and are not frequency-agile in the least. For such circuits to attain frequency agility, they must employ multiple VCXOs, one for each narrow band of clock frequency they may be called upon to generate. This further raises their cost and complexity.
Another approach employs a PLL in combination with a multi-tap delay-locked loop (DLL). DLLs are far less expensive than VCXOs and can be integrated into the same chip as PLLs. Further, their multiple taps yield frequency agility. Unfortunately, this type of PLL/DLL circuit does not have the spectral purity of a VCXO. Further, since each tap provides a discrete (noncontinuous) clock phase, hopping among the taps (as happens when the master clock frequency jitters) introduces quantization jitter into the local clock signal. For a fixed number of phase taps, the proportion of jitter induced by tap-hopping increases as frequency increases. Jitter can be held to within acceptable ranges only by decreasing the phase difference between each tap. However this requires the number of DLL taps to increase, forcing the clock signal generating circuit as a whole to be larger and more complex, expensive and power consumptive. Additionally, an increase in the number of DLL taps may restrict the maximum operational frequency of the local clock signal generating circuit.
Accordingly, what is needed in the art is a fundamentally new architecture for a local clock generating circuit. The circuit should ideally be integratable into a single chip, frequency-agile, introduce only acceptably low jitter, and should avoid the expensive, discrete-component VCXOs and low spectral purity or complex, many-tapped DLLs of the prior art.